Regviz

Silicon Labs /EFM32PG22C200F128IM32 /EMU_NS /RSTCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RSTCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/EMU_S/RSTCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)WDOG0RMODE 0 (DISABLED)SYSRMODE 0 (DISABLED)LOCKUPRMODE 0 (DISABLED)AVDDBODRMODE 0 (DISABLED)IOVDD0BODRMODE 0 (DISABLED)DECBODRMODE 0 (DISABLED)DCIRMODE

IOVDD0BODRMODE=DISABLED, DCIRMODE=DISABLED, SYSRMODE=DISABLED, AVDDBODRMODE=DISABLED, LOCKUPRMODE=DISABLED, WDOG0RMODE=DISABLED, DECBODRMODE=DISABLED

Description

No Description

Fields

WDOG0RMODE

Enable WDOG0 reset

0 (DISABLED): Reset request is blocked

1 (ENABLED): The entire device is reset except some EMU registers
SYSRMODE

Enable M33 System reset

0 (DISABLED): Reset request is blocked

1 (ENABLED): Device is reset except some EMU registers
LOCKUPRMODE

Enable M33 Lockup reset

0 (DISABLED): Reset Request is Block

1 (ENABLED): The entire device is reset except some EMU registers
AVDDBODRMODE

Enable AVDD BOD reset

0 (DISABLED): Reset Request is block

1 (ENABLED): The entire device is reset except some EMU registers
IOVDD0BODRMODE

Enable VDDIO0 BOD reset

0 (DISABLED): Reset request is blocked

1 (ENABLED): The entire device is reset except some EMU registers
DECBODRMODE

Enable DECBOD reset

0 (DISABLED): Reset request is blocked

1 (ENABLED): The entire device is reset
DCIRMODE

DCI System reset

0 (DISABLED): Reset request blocked

1 (ENABLED): The entire device is reset except some EMU registers

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data